In integrated circuit (IC) manufacturing, a semiconductor wafer typically contains a plurality of testlines in the scribe line area between adjacent wafer dies. Each testline includes a number of test devices, which are devices similar to those that are normally used to form the integrated circuit products in the wafer die area. By studying the parametric test results of devices on these testlines, it is possible to monitor, improve, and refine a semiconductor manufacturing process.
With the continuing scale-down of IC device feature sizes, integrated circuit device density and functional complexity are continuously increasing. This trend imposes new challenges on the existing parametric testline structure and test methodologies. One of these challenges is that the testlines of advanced technology devices must include a tremendous amount of test structures to meet the testing needs for advanced semiconductor devices and complex integrated circuits. However, the current testline structure can only support a limited number of test devices, as known to people skilled in the art.
Another challenge is that the parametric test results on existing testline devices are gradually losing their correlation with real integrated circuit performance, as technology advances. This is due to the fact that typical structures in semiconductor manufacturing only supply generic testline devices corresponding to a specific technology node, while the circuit designers/customers might integrate customized devices/circuits (for example, proprietary IPs) in their products for achieving specific circuit functions. In current practice, these customized devices are not presented and tested on a conventional testline due to the limited available spaces for test devices.
Another challenge is the need to design-for-manufacturability (DFM) in advanced technology. In current practice, library and test structure designers focus more on electrical characteristics than on layout styles due to their lack of visibility on the impact of layout styles on device manufacturing yield. In order to analyze the correlation of a specific layout style to a process yield and obtain a preferred set of library/test structure layouts leading to predictable manufacturing yield on an advanced technology generation, designers need much more testing resources on a testline than they are currently offered by a conventional testline.
Another limitation of conventional testlines can be appreciated by those skilled in the semiconductor R&D field. In semiconductor manufacturing, the mass production of an integrated circuit product normally follows a long period of pilot line development stage, during which extensive design-on-experiment (DOE) and statistical split activities are carried out to obtain the optimal process parameters and reach a process flow for high manufacturing yield. Conducting DOE and statistical split involves forming a large number of the test devices under different process conditions and obtaining the optimized process parameters by statistical analysis on the test results. Due to the limitation of available test device spaces on a conventional testline, a large quantity of test wafers are required in order to obtain reliable statistical results. Tuning a process flow in advanced technology demands more DOE and statistical split activities, which will have a significant impact on the cost of R&D.
In view of these and other issues in a conventional parametric testline and the ever increasing testing tasks demanded by advanced technologies, there is a need for improved testline structures capable of accessing a large number of test devices and conducting highly accurate parametric tests and methods of using the same.